`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:03:50 05/02/2014 
// Design Name: 
// Module Name:    slow_clock 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module slow_clock(	clk,rst,
							slow_clk  );
	input clk,rst;
	output slow_clk;

	//////////////////////////////////////////////////////////////////////////////////
	reg slow_clk;
	reg [11:0] count;
	
	initial begin
		count <= 0;
		slow_clk <=0;
	end
	
	always @ (posedge clk) begin
		if(rst) begin
			count <= 0;
		end
		else begin
			count <= count + 1'b1;
		end
	end
	
	always @ (posedge clk) begin
		if (	count == 2047 ) 
			slow_clk <= 1'b1;
		else
			slow_clk <= 0;	
	end
	//////////////////////////////////////////////////////////////////////////////////



endmodule
